The present invention relates generally to computer memory, and more specifically to wear-focusing of non-volatile memories.
Phase-change memories (PCMs) and flash memories are examples of non-volatile memories with limited endurance (also referred to as a “limited life”). Such memories have limited endurance in the sense that after undergoing a number of writing cycles (RESET cycles for PCM, program/erase cycles for flash memory), the memory cells wear out and can no longer reliably store information.
Not-and (NAND) flash memories are increasingly being used as non-volatile storage media in both consumer and enterprise applications. A fundamental constraint in these memories is the low endurance of each cell. Specifically, each cell can only be programmed (i.e. written to) and erased a very limited number of times, before it becomes potentially unusable. Further, the endurance of these memories has been decreasing as memory densities increase. For example, the latest multi-level cell (MLC) NAND devices have endurance specifications of only 3,000 to 5,000 program/erase cycles. The relatively low endurance of NAND flash is a major concern, especially in enterprise applications with stringent reliability requirements.
One technique used to prolong the lifetime of a flash device is wear-leveling. As the name suggests, wear-leveling seeks to make the amount of wear uniform across the cells of the memory by spreading writes evenly across the memory. A shortcoming of the wear-leveling approach is that it treats all memory regions and all data identically. Thus, once the entire memory has been cycled to the specified endurance limit, it is treated as potentially unusable. In reality, the endurance limit of flash is not a hard limit; instead as a cell is cycled more, its retention decreases and the probability of a bit error increases smoothly. Thus, there is a trade-off between data retention/cell-error and endurance.